1. Field of the Invention
The present invention pertains to a particular TaNx/Ta barrier/wetting layer structure which increases the degree of {111} crystal orientation in an overlying copper layer, thereby providing improved electromigration resistance of the copper.
2. Brief Description of the Background Art
As microelectronics continue to miniaturize, interconnection performance, reliability, and power consumption has become increasingly important, and interest has grown in replacing aluminum alloys with lower-resistivity and higher-reliability metals. Copper offers a significant improvement over aluminum as a contact and interconnect material. For example, the resistivity of copper is about 1.67 μΩcm, which is only about half of the resistivity of aluminum.
There are two principal competing technologies under evaluation by material and process developers working to enable the use of copper. The first technology is known as damascene technology. In this technology, a typical process for producing a multilevel structure having feature sizes (i.e., width of the aperture) in the range of 0.5 micron (μm) or less would include: blanket deposition of a dielectric material; patterning of the dielectric material to form openings; deposition of a diffusion barrier layer and, optionally, a wetting layer to line the openings; deposition of a copper layer onto the substrate in sufficient thickness to fill the openings; and removal of excessive conductive material from the substrate surface using chemical-mechanical polishing (CMP) techniques. The damascene process is described in detail by C. Steinbruchel in “Patterning of copper for multilevel metallization: reactive ion etching and chemical-mechanical polishing”, Applied Surface Science 91 (1995)139-146.
The competing technology is one which involves the patterned etch of a copper layer. In this technology, a typical process would include deposition of a copper layer on a desired substrate (typically a dielectric material having a barrier layer on its surface); application of a patterned hard mask or photoresist over the copper layer; pattern etching of the copper layer using wet or dry etch techniques; and deposition of a dielectric material over the surface of the patterned copper layer, to provide isolation of conductive lines and contacts which comprise various integrated circuits.
Typically, the copper layer can be applied using sputtering techniques well known in the art. The sputtering of copper provides a much higher deposition rate than evaporation or CVD (chemical vapor deposition) and provides a purer copper film than CVD.
In integrated circuit interconnect structures where copper is the material used to form conductive lines and contacts, it is recognized that copper diffuses rapidly into adjacent layers of SiO2 and silicon and needs to be encapsulated. Gang Bai et al. in “Copper Interconnection Deposition Techniques and Integration”, 1996 Symposium on VLSI Technology, Digests of Technical Papers (0-7803-3342-X/96, IEEE), describe the effectiveness of Ta, TiN, W and Mo as barrier layers for use with copper. They concluded that Ta annealed in UHV (ultra high vacuum) after copper deposition provided the best barrier layer. Sputtered copper appeared to be preferable over CVD copper and over electroplated copper, although all the data for electroplated copper was not available at the time of presentation of the paper.
U.S. Pat. No. 4,319,264 of Gangulee et al., issued Mar. 9, 1982 and titled “Nickel-gold-nickel Conductors For Solid State Devices” discusses the problem of electromigration in solid state devices. In particular, the patent discusses the application of direct current over particular current density ranges which induces motion of the atoms comprising the thin film conductor, the effect known as electromigration. Electromigration is said to induce crack or void formation in the conductor which, over a period of time, can result in conductor failure. The rate of electromigration is said to be dependent on the current density imposed on the conductor, the conductor temperature, and the properties of the conductor material. In high current density applications, potential conductor failure due to electromigration is said to severely limit the reliability of the circuit. In discussing the various factors affecting performance of the conductive materials, grain structure is mentioned as being important. (In order to obtain adequate lithographic line width resolution, it is recommended that the film be small grained, with a grain size not exceeding about one-third of the required line width.) Uniformity of grain size and preferred crystallographic orientation of the grains are also said to be factors which promote longer (electromigration limited) conductor lifetimes. Fine grained films are also described as being smoother, which is a desirable quality in semiconductor applications, to lessen difficulties associated with covering the conductor with an overlayer.
U.S. Pat. No. 5,571,752 to Chen et al., issued Nov. 5, 1996, discloses a method for patterning a submicron semiconductor layer of an integrated circuit. In one embodiment describing an aluminum contact, titanium or titanium nitride having a thickness of between approximately 300 and 2,000 Å is formed by sputter deposition to reach the bottom of a contact opening. Finally, a second conductive layer, typically aluminum, is applied over the surface of the conformal conductive layer. The aluminum is sputtered on, preferably at a temperature ranging between approximately 100° C. and 400° C. This method is said to make possible the filling of contact openings having smaller device geometry design requirements by avoiding the formation of fairly large grain sizes in the aluminum film.
As described in U.S. patent application Ser. No. 08/824,911, of Ngan et al., filed Mar. 27, 1997 and commonly assigned with the present invention, efforts have been made to increase the <111> crystallographic content of aluminum as a means of improving electromigration of aluminum. In particular, the <111> content of an aluminum layer was controlled by controlling the thickness of various barrier layers underlying the aluminum layer. The underlying barrier layer structure was Ti/TiN/TiNx, which enabled aluminum filling of high aspect vias while providing an aluminum fill exhibiting the high degree of aluminum <111> crystal orientation. The Ti/TiN/TiNx barrier layer was deposited using IMP (ion metal plasma) techniques, and the barrier layer thicknesses were as follows. The thickness of the first layer of Ti ranges from greater than about 100 Å to about 500 Å (the feature geometry controls the upper thickness limit). The thickness of the TiN second layer ranges from greater than about 100 Å to less than about 800 Å (preferably, less than about 600 Å). And, the TiNx third layer (having a Ti content ranging from about 50 atomic percent titanium to about 100 atomic percent titanium) ranges from about 15 Å to about 500 Å. A Ti/TiN/TiNx barrier layer having this structure, used to line a contact via, is described as enabling complete filling of via with sputtered warm aluminum, where the feature size of the via or aperture is about 0.25 micron or less and the aspect ratio ranges from about 5:1 to as high as about 6:1.
Subsequently, in U.S. Pat. No. 5,882,399, of Ngan et al., issued Mar. 16, 1999, the inventors disclose that to maintain a consistently high aluminum <111> crystal orientation content of an interconnect during the processing of a series of semiconductor substrates in a given process chamber, it is necessary to form the first deposited layer of the barrier layer to a minimal thickness of at least about 150 Å, to compensate for irregularities in the crystal orientation which may be present during the initial deposition of this layer when the process chamber is initially started up (and continuing for the first 7-8 wafers processed). Ngan et al. teach that in the case of a copper conductive layer, it may also be necessary that the first layer of a barrier layer structure underlying the copper layer have a minimal thickness of at least about 150 Å, to enable a consistent crystal orientation within the copper layer during the processing of a series of wafers in a semiconductor chamber.